hi-sincerity microelectroni c s corp. spec. no. : ic20 0803 issued date : 20 08.09.10 revised date : page no. : 1/6 h6842p, h684 2 s hsmc product s pecification h6842p / H6842S novel low cost green -pow er pw m controlle r description 8-lead plastic dip-8 package code: p t he h684 2 is a lo w sta r tu p cu rrent, lo w co st, curre n . mode pwm co ntrolle r w i th gre en-po w e r & burst- mo d e p o w e r-sav i ng op eration. t he in teg r ated fun c tio n s su c h as the le a d i ng - e dge bla nk i n g of the cu rre nt se nsing, i nternal sl o p e com pe n sation provid e the u s e r s a hi g h ef ficien c y , lo w ext e rn a l com p on e nt cou nts, an d lo w c o st solution for a c /dc po w er app li catio ns. t he spe c ial gre en-p o w e r functio n p r ov id e s off-time mod u latio n to linea rly de cre a se the s w it chin g f r eque n c y un der ight-load con d ition s . and u n de r zero-lo a d con d ition s , the po w e r s u p p ly e n t e rs b u r s t-mo de to fur t he r redu c e po w e r co n s umption b y sh utting off p w m o u tput. w h e n the o u tp u t of p o w e r s u pp ly is sho r t or o v er lo a d e d , th e fb voltag e w i ll incre a se, an d if the fb voltage is hi ghe r than 5.2v f o r longer th an 56msec the pwm out put w ill be turned off. 8-lead plastic so-8 package code: s ? a ex ternal ntc resi sto r co nne cted from pin rt to g r o und ca n b e applie d to over- tempe r atu r e prote c tio n . pu lse b y p u l s e current limit ensu r e s a con s tant ou tpu t cu rre nt e v e n under sh ort circuit. pwm output w i ll be disabled a s long as vdd ex ce e d s a th re sh old . wh en in ternal latc h ci rcui t is us ed to latch-off the co ntrolle r the lat c h w i l be re se t w h en the po w e r su pp ly vdd i s d i sable d features ? low cost, green-power burst-mode pwm ? ver y lo w start - up curr e n t ( about 7.5u a) applications ? p o w e r a d a p t o r ? open f r ame s w itc h in g po w e r su ppl y ? b a t t e r y c h a r g e r a d a p t e r ? lcd monitor ordering information part number description h6842p dip-8, pb-free in tube H6842S sop-8, pb-free in tube H6842Sa sop-8,pb-free in t/r ? low operating current ( about 3.0ma) ? current mode operation ? under voltage lockout (uvlo) ? vdd over voltage protection(ovp) ? programmable over-temperature protection ? internal latch circuit(otp,ovp) ? built-in soft start with 1ms ? soft clamped gate output voltage 16.5v ? vdd over voltage protect 25.5v ? cycle-by-cycle current limiting ? output scp (short circuit protection) ? built-in synchronized slope ompensation ? leading-edge blanking on sense input ? programmable pwm frequency ? high-voltage cmos process with esd ? dip-8 & sop-8 pb-free package ? compatible with sg6842j&ld7552& ob2269 & sg6841 & ob2268 http://
hi-sincerity microelectroni c s corp. spec. no. : ic20 0803 issued date : 20 08.09.10 revised date : page no. : 2/6 h6842p, h684 2 s hsmc product s pecification pin connection (top view) package function description pin1: gnd gnd pin pin2: fb voltage feedback pin. the pwm duty cycle is determined by fb and sense. pin3: vin this pin is pulled high to the rectified lin e input through a large resistor for start-up. this pin is also used to detect line voltage to compensate for constant output power limit for universal ac input. pin4: ri by connecting a resistor to ground to set the switching freq. increasing the resistor will reduce the switching freq. pin5: rt an nt c resis t or is con nect ed from this pin to gro u n d for o v er-tem peratur e protection. pin6: sense current se ns e pin, t he sen s ed vo lt age is used for curr ent-mod e cont rol an d p u ls e - b y -p u l s e current limiti ng. pin7: vdd power supply voltage pin. 12 3 4 5 6 7 8 dip-8 12 3 4 5 6 7 8 so-8 pin8: gate gate drive o u t put to driv e th e e x t e rn al mo sf et . a s o ft driving wavefo rm isimpleme n ted to improve e mi. typical application circuit block diagram
hi-sincerity microelectroni c s corp. spec. no. : ic20 0803 issued date : 20 08.09.10 revised date : page no. : 3/6 h6842p, h684 2 s hsmc product s pecification absolute maximum ratings symbol parameter value unit v dd supply voltage pin vo l t a g e 40 v v fb input voltage to fb pin -0.3 to 6v v v sens input voltage to sense pin -0.3 to 6v v p d power dissipation 1000 mw esd capability, hbm model 2000 v esd capability, machine model 200 v dip-8 10sec 260 t l lead temperature(soldering) sop-8 10sec 230 o c t j storage temperature range -55 to + 150 o c t stg lead temperature (soldering 10s) 300 o c electrical characteristics ( ta=25c unless otherwise noted, v dd = 15v. ) symbol parameter conditions min. typ. max. unit supply voltage (v dd pin) i st startup current vdd= 15v 7.5 30 a i ss operating current vfb=vsense= 0v vdd= 15v 3 5 ma v th(on) start threshold voltage -- 16 16.5 17 v v th(off) min. operating voltage -- 10.4 10.8 11.2 v vdd over voltage vdd-ovp protecti on(latch off) 23 24.5 25 v vdd low-threshold voltage vdd-th-g to exit green-off mode 11 12 13 v voltage feedback (fb pin) i fb short circuit current v fb =0v 1.42 ma v fb open loop voltage v fb =open 6 v current sensing (sen pin) v th threshold voltage for current limit i vin =0 0.76 0.9 v t pd delay to output 115 200 nsec z cs input impedance 13 k ? b nk leading edge blanking time 260 354 460 nsec oscillator (ri pin) f osc frequency in nominal mode ri=26k ? 63 67 70 khz f osc-green frequency in green mode ri=26 k ? 25 27 29 khz beginning of frequency v n reducing at fb voltage vdd=15v 1.95 2.05 2.15 v end of frequency reducing at v g fb voltage vdd=15v 1.5 1.54 1.6 v g
hi-sincerity microelectroni c s corp. spec. no. : ic20 0803 issued date : 20 08.09.10 revised date : page no. : 4/6 h6842p, h684 2 s hsmc product s pecification frequency temp. stability -30-85 5 % gate drive output (gate pin) v ol output low level vdd=12v,i o =50ma 0.32 0.6 v v oh output high level vdd=12v,i o =50ma 7.2 8 v t r rising time vdd=15v,c l =1nf 200 240 280 ns t f falling time vdd=13v,c l =1nf 30 80 90 ns dc max maximum duty cycle 84 86 88 over-temperature protection section i rt output current of pin rt ri=26k ? 65 70 75 a v otp thre sh old vol t age for over- temperature protection. 1 1.05 1.1 v ri section ri nor ri operating range 15.5 26 36 k ? ri max max ri value for protection 216 k ? ri min 6 k ? note 1: adjust v cc above the start threshold before setting at 15v. note 2: these parameters, although guaranteed are not 100% tested in production. note 3: parameter measured at trip point of latch with v pin2 =0. note 4: gain defined as: a=v pin1 /v pin3 , 0 d v pin3 d 0.8v operation description start-up current & operating current the typical start-up current is only 8 a. this allows a high resistance, low-wattage start-up resistor to be used to minimize power loss a 1.5mohms , 0.25w, start-up resistor and a 10 f/40v vdd hold-up capacitor would be sufficient for an ac/dc adapter with a universal input range the re quire d ope ratin g cu rre nt has be e n redu ce d t o 3.4ma. thi s re sult s in hi ghe r effici en cy and re du ce s the vdd hold-up capacitance requirement green-power mode operation the prop ri e t a r y gree n-po wer mo d e fun c tio n provide s off-time modu l a tion to conti nuou sly de crea se th e pwm freq ue n c y un de r light-lo ad con d ition s . to avoid a c ou stic-n oi se p r obl em, the minimum pwm freque n c y set above 25 khz. thi s gree n-po wer mode fun c tio n dramati c all y r educe s p ower con s u m ption un d er li ght -loa d a n d ze ro-l oa d con dition s . powe r su pp li es u s ing a h68 42 co ntrolle r ca n ea sily me et even the mo st restri ctive international reg ul ation s re garding sta n dby po we r co n s um ption. oscillator operation a re sisto r co nne cted from the ri pin t o g n d pin gen e r at e s a co nsta nt current sou r ce for the h68 42 co ntro lle r this c u rr ent is used to det er mine the c e nter p w m fr equenc y. inc r eas ing the r e s i s t ance w ill reduc e pw m frequ en cy.usi ng a 26k ? re si st o r r i r e s u lt s in a c o r r e s p on d i ng 6 7 k h z pw m fr equen c y .t he re latio n s h i p be tw e e n r i and the swi t chin g freq ue ncy is .th e frequ e n cy variation ra nge s from a r ou n d 63khz to 70khz for a center freq u e ncy 67 khz.t he emi enhancemen t f u n c t i o n h e l p s r e d u c e e m i e m i s s i o n o f a p o w e r s u p p l y w i t h minimum line filters leading edge blanking each time the power mosfet is swit che d on, a turn-on spi k e will inevitably oc cur at the sense-resi stor. to avoid premat u r e termi nati on of the swit chin g pul se, a lea d ing-edg e blanki ng ti me is built in. during thi s blan king peri o d,the cu rre n t -limit com pa r ator i s di sa bl ed, an d it ca nn ot swit ch of f the gate drive. under-voltage lockout (uvlo)
hi-sincerity microelectroni c s corp. spec. no. : ic20 0803 issued date : 20 08.09.10 revised date : page no. : 5/6 h6842p, h684 2 s hsmc product s pecification the turn-on/turn-off thresholds are fixed internally at 12.4v/16.5v. to enable a h6842 controller during start-up, the hold-up capacitor must first be charged to 16.5v through the start-up resistor. the hold - u p cap acito r will contin ue to supply vdd before energy can be deli v ered f r om the auxiliary wi nd i ng of th e main tran sform e r. vdd must not drop b e lo w 1 2 .4 v durin g t h is s t ar t- u p pr oc e s s . t h is u v lo h y s t ere s i s w i n dow ens ure s that t he hol d-u p ca p acito r ca n adequ ately supply vdd du ri n g start - up. gate output / soft driving the h6842 output stage is a fast totem pole gate driver . cross-conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. the output driver is clamped by an internal 18v zener diode in order to protect the power mosfet transistors from any harmful over-voltage gate signals. a soft driving waveform is implemented to minimize emi. slope compensation the se nsed voltage acro ss the cu rrent sen s e re si sto r is u s e d for pea k-cu rre nt-m ode co ntrol and cy cle - by -c y c l e cu rrent lim itin g. the b u ilt-in sl ope comp e n s atio n fun c tio n i m prove s p o we r su pply stability and p r event s p ea k -cu r re nt - mo de co ntrol from ca usi ng sub - h arm oni c oscillation s. within eve r y swit ch ing cycl e, the h6 842 cont roll e r pro d uces a p o sitively slop ed, synch r o n ized ramp sign al constant output power limit whe n the sense voltage a c ro ss the se nse r es i s t o r r s reache s th e threshol d vo l t age, the output gate d r ive w ill be tur n ed off follow ing a s m all pr opagation delay t pd . this propagation del ay will result in an addition al cu rre nt prop o r tio nal to t pd *v in /l p . the pro p a g a tio n d e lay is ne a r ly co n s tant re g a rdle ss of th e input line v o ltage v in . high er i nput l i ne voltage s will re su lt in large r a d dit i onal cu rre n ts. thu s , u nder hi gh inp u t -lin e voltage s the out put power li mit will be hi gher than under lo w input-line voltage s. the output power limit variation can be significant ov er a wide range of ac input voltages. to compensate for this, the th re shold volta g e is adju s ted by the cu rrent i in . since the pin vin is con n e c te d to the re ctified i n put line voltage through the start- up resistor, a higher line voltage will result in a higher current i in through the pin vin. the thre sh ol d voltage de cre ases if th e cu rrent i in increa se s. a small thre sh o l d voltage will force the out put gat e drive to terminate e a r lie r, thu s re du cin g total pwm turn-o n time, and m a kin g the out put po we r eq ual to to that of the low line input. this proprietary internal compensation feature ensures a constant output power limit over a wide range of ac input voltages (90vac to 264vac) vdd over-voltage protection vdd ove r-v ol tage prote c t i on ha s be en built in to prevent dam a ge d ue to ove r voltage con d ition s . whe n the v o ltage v dd excee d s the internal threshold due to abnormal condition s , pwm out put wi ll be turned off. over-voltage con d ition s are usu a lly cau s e d by op en fee dba ck lo op s. limited power control the fb voltage will i n crea se every time the output of the po wer sup ply is sh orted or over-load ed. if the fb voltage rem ai n s hig he r tha n a built-in thresh old fo r lo n ger tha n t lps , pwm output will then be turned off. as pwm output is turned off, the supply voltage vdd will also begin decreasi ng. when vdd goes bel ow the turn-off threshold (eg, 12.4v) the c ontroll er will be totally shut down. vdd will be charged up to t he t u rn-on thresh ol d voltage of 16. 5v thro ug h the sta r t-up re si sto r until pwm output is re starte d. thi s protectio n feature will co ntin ue to be activated as long as the over-loading condition persi sts. this will prevent the power supply from overheating due to over loading conditions thermal protection an external ntc the r mi sto r can be con n ected f r o m th e rt pi n to grou nd. a fixed cu rre n t i rt i s s o u r c ed from the rt pin. beca u s e the imp e d a n ce of the ntc will de cre a se at high te mpe r ature s , whe n the voltage of the rt pin drops below 1.065v, pwm output will be disabled. the rt pin output current is related to the pwm frequency programming resistor r i. noise immunity noise from the current sense or the control signal may cause significant pulse width jitter, particularly in continuous-conduction mode. slope compensation helps alleviate this problem. good placement and layout practices should be followed. the designer should avoiding long pcb traces and component leads. compensation and filter components should be located near the h6842. finally, increasing the power -mos gate resistance is advised.
hi-sincerity microelectroni c s corp. spec. no. : ic20 0803 issued date : 20 08.09.10 revised date : page no. : 6/6 h6842p, h684 2 s hsmc product s pecification dip-8 dimension a b 87 65 4 3 2 1 h i f g j k m l 1 e d c 8-lead dip-8 plastic package hsmc package code: p marking: date code control code hp 6842 pb fr ee mar k pb -f re e : " . " ( n ot e) n o r m al : n one note: green label is used for pb-free packing pin st y l e: 1. gnd 2.fb 3. vi n 4. ri 5.rt 6.sense 7.v d d i 8.g a te material: ? lead solder plating: sn60/pb40 (normal), sn/3.0ag/0.5cu or pure-tin (pb-free) ? mold compound: epoxy resin family, flammabilit y solid burnin g class: ul94v-0 dim min. max. a 6.29 6.40 b 9.22 9.32 c - *1.52 d - *1.27 e - *0.99 f 3.25 3.35 g 3.17 3.55 h 0.38 0.53 i 2.28 2.79 j 7.49 7.74 k - *3.00 l 8.56 8.81 m 0.229 0.381 94 o 97 o 1 *: typical, unit: mm so-8 dimension a b f c d e g part a i h j k o m l n part a 234 5 6 7 8 pin1 index dim min. max. a 4.85 5.10 b marking: note: green label is used for pb-free packing 3.85 3.95 c 5.80 6.20 d 1.22 1.32 e 0.37 0.47 f 3.74 3.88 g 1.45 1.65 h 4.80 5.10 i 0.05 0.20 j 0.30 0.70 pin st y l e: 1. gnd 2.fb 3. vi n 4. ri 5.rt 6.sense 7.v d d i 8.g a te k 0.19 0.25 l 0.37 0.52 material: ? lead solder plating: sn60/pb40 (normal), sn/3.0ag/0.5cu or pure-tin (pb-free) ? mold compound: epoxy resin family, flammabili ty solid b u rning c la ss: ul94 v 0 m 0.23 0.28 n 0.08 0.13 o 0.00 0.15 *: typical, unit: mm 8-lead so-8 plastic surface mounted package hsmc package code: s important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of hsmc. ? hsmc reserves the right to make changes to its products without notice. ? hsmc semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? hsmc assumes no liability for any consequence of customer prod uct design, infringement of paten ts, or application assistance. head office and factory: ? head office (hi-sincerity microelectronics co rp.): 10f.,no. 61, sec. 2, chung-shan n. rd. taipei taiwan r.o.c. tel: 886-2 - 25212 056 fax: 886-2 - 2563 2712, 253684 54
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